Computer systems and integrated circuit processors exist which implement transactions with the dispatch and receipt of packets. Request packets define an operation to be performed and response packets indicate that a request has been received and whether or not the operation defined in the request packet has been successfully carried out. The integrated circuit processor can comprise a plurality of functional modules connected to a packet router for transmitting and receiving the request and response packets. Each functional module is connected to the packet router via a respective port. The increasing ability to incorporate a greater number of more complex modules on a single chip means that it is now possible to integrate a high performance CPU with a number of complex modules using a high performance bus in a system on a chip. Generally, the design process is such that the architecture of a processor is designed and the functional modules which are required are determined. Then, ports have to be designed for the functional modules to connect the functional modules to a packet router of the integrated circuit.
The complexity of the port depends on the complexity and functionality of the functional module which is to be attached to the packet router by the port. In principle therefore it is either necessary to design a port to match the functionality of each functional module, or to constrain the functional modules which can be connected to a packet router by the ports which have been designed.
It is an aim of the present invention to provide connection ports with enhanced functionality which are preferably based around a common port primitive. This simplifies port design and selection and also allows the common packet protocol to be used for communication of packets across the packet router.